1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a top gate type thin film transistor and a method of manufacturing the same.
2. Description of the Related Art
Generally, a polysilicon (poly-Si) thin film transistor has excellent current driving capability and a fast operating speed as compared to an amorphous silicon thin film transistor. Due to these advantages, a poly-Si thin film transistor has been recently used as a switching device for a display device or a driving circuit. A conventional poly-Si thin film transistor is formed on a semiconductor substrate comprising a source region, a drain region, and a channel region, and a gate structure that contacts the source and drain regions is formed on the channel region. The gate structure comprises a gate insulating layer and a gate electrode layer that is electrically insulated by the gate insulating layer from a semiconductor layer.
In a conventional method of manufacturing a poly-Si thin film transistor, since the source and drain regions are formed through an ion implantation process using a gate electrode as a self-aligning mask, the source and drain regions are adjacent to the channel region. Thus, in an off state in which a voltage applied to the source or drain region is higher than a voltage applied to a gate electrode layer, a vertical electric field is generated in the source or drain region in a direction of the gate electrode. Since a carrier captured in a depletion region is excited by the electric field and thereby escapes from the depletion region, a leakage current may occur. Due to the leakage current, the on/off switching of a device is difficult, and the display quality of an active matrix liquid crystal display (AMLCD) or an active matrix organic light emitting diode (AMOLED) may be degraded.
In order to address the above-described problems, a new structure for dispersing a drain electric field has been suggested. A lightly doped drain (LDD) or offset structure having a predetermined resistance is formed between the gate structure and the source and drain regions to act as a kind of resistance for disturbing the flow of the leakage current. Thus, a reduction in the leakage current may be expected. However, in a method of manufacturing such a structure, an additional mask is required to form the LDD or offset structure and self-alignment does not occur. In addition, a doping process should be performed twice to form the source and drain regions and the LDD structure. Thus, it is difficult to guarantee the uniform characteristic of a thin film transistor. Also, since the method of manufacturing the structure is complicated, the manufacturing cost increase, yield is reduced, and a device characteristic may be lowered.